This invention relates generally to graphene, and more particularly relates to graphene synthesis.
Over the past four decades, a reduction in the size of silicon metal-oxide-semiconductor field effect transistors (MOSFETs) has been one key to the progress that has been achieved in producing advanced microfabricated, integrated electronics. But as the limit of size scaling is approached for such silicon electronics, silicon microfabrication process have become highly complicated; consequently, a demand for the simplification of fabrication processes and the use new materials, beyond silicon, has been rapidly rising for the next generation of circuits.
One proposed strategy for minimizing the intensive steps of conventional CMOS fabrication processes such as lithography, ion-implantation, annealing, deposition, and etching, is the co-synthesis of all elements in an integrated circuit. A conceptually similar approach, albeit employing chemical synthesis of individual device elements, rather than entire integrated structures, was initiated in the research field of one-dimensional (1D) nanowire/nanotubes. However, the nature of 1D materials requires assembly and additional integration steps, such as metallization, to yield integrated electronics.
Of the potential new materials to be considered for next generation circuitry, graphene is for many applications the most promising. Graphene is a single two-dimensional atomic layer of sp2-bonded carbon atoms. The vertical stacking of multiple layers of monolayer graphene constitutes graphite. Graphene has attracted the attention of the materials and electronic device communities as one of the best candidate materials for post-silicon microfabrication as a result of high carrier mobility. In addition, graphene is characterized by superb electric and mechanical properties, thermal conductivity, and optical transparency.
These characteristics of graphene have led to the rapid development of processes for the synthesis of graphene, for example, by the reduction of graphene oxide, by epitaxial graphene growth out of SiC, and by chemical vapor deposition (CVD) synthesis using metal catalysts. In general, conventional graphene synthesis processes are optimized to enable formation of a layer of graphene that under select process conditions is uniform across a large area. But such processes do not address the specific materials requirements for fabricating a range of device components based on graphene materials, such as FETs and electrical interconnects. The full potential of graphene as a microfabrication material cannot be achieved until the requirements for microfabrication of graphene devices, such as FET devices and interconnects, are met.